Digital Logic | Processor Design

Simple RISC Machine

I designed a 16-bit multi-cycle processor in SystemVerilog. I built the register file, ALU, operand shifter, datapath, instruction decoding logic, finite state machine controller, and status-flag logic, then wrote RTL testbenches to verify individual modules and end-to-end instruction execution.

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16-bit datapath
8 × 16-bit registers
4 ALU operations
4 shift modes
N / V / Z flags
Multi-cycle control
RTL Project

Processor Design & Verification

Simple RISC Machine SystemVerilog processor project
01

Architecture

I separated the processor into a datapath and a multi-cycle controller. The controller decodes the instruction fields and generates the control signals required to move operands through the datapath over several clock cycles.

The datapath contains the register file, operand registers, shifter, ALU, result register, status logic, and the multiplexers used to select register addresses, immediate values, and write-back data.

Instruction
opcode, op, Rn, Rd, shift, Rm, immediate
Decoder + FSM
control sequencing
Register File + Operands
data storage and operand selection
Shifter + ALU
execution, flags and write-back
Control

Multi-Cycle FSM

Instructions move through a sequence of states so operand loading, execution, write-back, and flag updates occur on separate cycles.

Datapath

16-Bit Data Path

Register values, operands, immediates, and ALU results are represented as 16-bit values.

Storage

Eight General Registers

The register file contains eight 16-bit registers with combinational read and synchronous write behavior.

Status

N / V / Z Flags

The datapath tracks negative, signed overflow, and zero conditions for arithmetic and comparison operations.

02

Instruction Decoding

The controller extracts fields directly from the 16-bit instruction register and uses them to select register addresses, ALU operations, shift behavior, and immediate values.

Opcode
Bits [15:13]
Operation
Bits [12:11]
Rn
Bits [10:8]
Rd
Bits [7:5]
Shift
Bits [4:3]
Rm
Bits [2:0]
Immediate
Immediate fields are sign-extended to the 16-bit datapath before they are used.
03

Register File

I implemented an eight-entry, 16-bit register file. Register values can be read combinationally while writes occur synchronously when the controller asserts the register write enable.

The register-selection logic chooses between Rm, Rd, and Rn depending on which register field is needed at that stage of instruction execution.

Capacity

8 × 16 Bits

Eight general-purpose storage locations, each containing one 16-bit value.

Timing

Synchronous Write

New data is written into the selected register on the active clock edge when write is enabled.

04

ALU & Shifter

The processor uses a separate operand shifter before the ALU. This allows a source operand to be shifted before being used by an arithmetic or logic operation.

ALU Select Operation
00 A + B
01 A - B
10 A AND B
11 NOT B
No Shift
Operand passes through unchanged.
LSL #1
Logical left shift by one bit.
LSR #1
Logical right shift by one bit.
ASR #1
Arithmetic right shift by one bit.
05

Status Flags

The datapath generates three status conditions used during arithmetic and comparison operations.

Z

Zero

Asserted when the ALU result is zero.

N

Negative

Derived from the most significant bit of the signed ALU result.

V

Overflow

Detects signed overflow during addition and subtraction operations.

06

Verified Instructions

At the CPU level, I exercised the instruction paths implemented by the current controller and verified their register, arithmetic, shift, logic, and status behavior.

Instruction Verified Behavior
MOV Rn, #imm8 Sign-extended immediate value written directly into the selected register.
ADD Register arithmetic, including shifted source operands.
AND Bitwise AND between register operands.
MVN Bitwise inversion of the source operand, including shifted operand behavior.
CMP Subtraction-based comparison with N, V, and Z status updates.
07

Multi-Cycle Control

The finite state machine sequences instructions over multiple clock cycles so register reads, operand loading, ALU execution, write-back, and status updates happen at the correct time.

ADD / AND / MVN: Wait → Decode → GetB → ALUOp → WriteReg → Wait
CMP: Wait → Decode → GetB → ALUOp → UpdateFlags → Wait
MOV immediate: Wait → WriteImm → Wait
08

RTL Verification

I tested the design at both the module and CPU levels. The ALU, register file, and shifter were exercised separately before checking complete instruction execution through the integrated processor.

Module

ALU Tests

Verified addition, subtraction, AND, inversion, zero detection, sign behavior, and overflow cases.

Module

Register File Tests

Checked addressing, synchronous writes, combinational reads, and stored register values.

Module

Shifter Tests

Verified pass-through, logical left, logical right, and arithmetic right shifts.

System

CPU Instruction Tests

Exercised immediate moves, shifted arithmetic, logic operations, MVN, and CMP status behavior through the full processor.

09

RTL Structure

cpu.sv
Instruction register, decoding logic, multi-cycle FSM, control generation, and datapath integration.
datapath.sv
Operand registers, muxes, register file, shifter, ALU, result register, and status logic.
ALU.sv
Arithmetic and bitwise execution logic with status calculations.
regfile.sv
Eight-entry 16-bit register file.
shifter.sv
Four operand shift modes.
Testbenches
RTL tests used to verify individual modules and end-to-end processor behavior.
10

Tools & Skills

This project gave me hands-on experience building a processor from individual RTL blocks and reasoning about how control logic, timing, storage, arithmetic, and verification fit together as a complete digital system.

SystemVerilog RTL Design CPU Architecture Multi-Cycle FSM Register File ALU Shifter Status Flags RTL Verification ModelSim FPGA