I am building a small 16-bit processor in SystemVerilog to learn more about RTL design, processor architecture, and parallel hardware. I started with the basic scalar blocks and am now adding a four-lane SIMD execution path.
The goal is to build a small processor where I can follow an instruction from fetch and decode all the way through the register file and execution hardware. The first version supports a basic scalar ALU, and the next part adds SIMD so one instruction can operate on four packed values in parallel.
I am keeping the design small on purpose so I can understand every block, simulate it separately, and then connect the whole processor together before moving on to synthesis and timing analysis.
The processor starts with an 8-bit program counter. The program counter selects a 16-bit instruction from instruction memory, the decoder breaks the instruction into control and register fields, and the register file provides two operands to the execution hardware.
I am currently using one bit to select scalar or SIMD execution, three bits for the instruction class, three register-address fields, and a three-bit function field.
The current ALU function codes are 000 = ADD, 001 = SUB, 010 = AND, and 011 = OR. Bit 15 selects whether the operation uses the scalar or SIMD execution path.
alu.sv
16-bit combinational scalar ALU supporting ADD, SUB, AND, and OR.
regfile.sv
Eight 16-bit registers with two combinational read ports, one synchronous write port, and R0 fixed at zero.
instruction_decoder.sv
Breaks the 16-bit instruction into register fields and generates ALU, write-enable, SIMD, and validity control signals.
program_counter.sv
8-bit sequential program counter that resets to zero and advances through instruction addresses.
instruction_memory.sv
Stores the 16-bit instructions used to bring up and test the processor.
processor_top.sv
Connects the processor blocks into the complete datapath. Scalar integration is being completed before the SIMD result path is added.
simd_lane.sv
Planned 4-bit lane that will implement the same basic operations as the scalar ALU.
simd_unit.sv
Planned four-lane execution block. All four lanes receive the same operation while working on different packed data.
I am building and testing the processor one block at a time. I will update this page as the SIMD datapath, full-core simulation, synthesis, and benchmarking are completed.
As the processor gets further along, I want the project page to show the actual engineering results rather than generic FPGA images.
Final block diagram showing fetch, decode, register file, scalar ALU, SIMD lanes, result selection, and writeback.
A cropped waveform showing one instruction being decoded and executed, with a short caption explaining what the signals prove.
RTL schematic plus timing and utilization results once the design is synthesized.